1. Field of the Invention
Example embodiments of the present invention relate to methods of manufacturing semiconductor devices. More particularly, the present invention relates to methods of manufacturing cell capacitors of dynamic random access memory devices.
2. Description of the Related Art
The capacitor area available for storing data shrinks, as the integration of dynamic random access memory (DRAM) that includes a capacitor increases. Recently, the DRAM has operated with a relatively low voltage. In addition, since the DRAM still employs a data sensing method, the capacitor included in the DRAM has to be above about 25 femtofarads (fF) to about 30 fF. However, capacitance above this range becomes difficult to achieve as the integration of the DRAM increases.
In general, when the area of the lower electrode decreases, the capacitance of the capacitor decreases. Thus, in order to overcome disadvantages due to the tendency of the capacitance to decrease, the height of the lower electrode may be varied. In addition, a dielectric layer having a substantially high dielectric constant may be employed in the capacitor.
Recently, cylindrical capacitors have been widely used to increase the capacitance of the capacitor. The cylindrical capacitor includes a lower electrode and a capacitor contact pad. The capacitor contact pad electrically contacts the lower electrode. However, since a design rule of the DRAM device has decreased, the capacitor contact pad may not easily contact the lower electrode.
FIGS. 1A to 1F are cross-sectional views illustrating a method of manufacturing a conventional DRAM capacitor.
Referring to FIGS. 1A to 1B, a semiconductor substrate includes an active region 100 and a field region 110. A first lower insulation interlayer 120a is formed on the active region 100 and the field region 110. A bit line 130 is then formed on the first lower insulation interlayer 120a. 
Referring to FIG. 1C, a first upper insulation interlayer 120b is formed on the first lower insulation interlayer 120a to cover the bit line 130. The first lower insulation interlayer 120a and the first upper insulation interlayer 120b are included in a first insulation interlayer 120. A contact pad 140 is formed through the first lower insulation interlayer 120a and the first upper insulation interlayer 120b. 
Referring to FIG. 1D, an etch stop layer 150 is formed on the first insulation interlayer 120. The etching stop layer 150 may have an etch rate substantially different from that of a second insulation interlayer 160 to be formed thereon. In general, the etch stop layer 150 may include silicon nitride. The second insulation interlayer 160 is then formed on the etch stop layer 150. Thereafter, a photolithography process is performed on the second insulation interlayer 160 and the etch stop layer 150 so that an electrode hole 170 is formed through the second insulation interlayer 160 and the etch stop layer 150. Since an etch rate of the etch stop layer 150 is substantially different from that of the second insulation interlayer 160, a lower portion of the electrode hole 170 may be substantially small.
Referring to FIGS. 1E and 1F, a lower electrode layer (not shown) is uniformly formed on an upper face of the second insulation interlayer 160 and an inner face of the electrode hole 170. A sacrificial layer (not shown) is then formed on the lower electrode layer so that the electrode hole 170 partially filled with the lower electrode layer may be fully filled with the sacrificial layer.
Thereafter, a polishing process such as a chemical mechanical polishing process is performed on the sacrificial layer and the lower electrode layer until the second insulation interlayer 160 is exposed. Thus, a lower electrode 180 and a sacrificial layer pattern 190 may be formed in the electrode hole 170. The sacrificial layer pattern 190 and the second insulation interlayer 160 are then removed.
Subsequently, a dielectric layer 192 and an upper electrode 194 are formed on the lower electrode 180. Since the lower portion of the lower electrode hole 170 is substantially narrow, an inner diameter of a lower portion of the lower electrode 180 may be substantially small. In addition, a thickness of the lower electrode 180 may be irregular. Thus, the dielectric layer 192 and the upper electrode may not efficiently cover an inner surface of the lower electrode 180.
FIG. 2 is an SEM picture illustrating the conventional cylindrical capacitor in FIG. 1F. Referring to FIG. 2, a lower portion of a lower electrode has a substantially small inner diameter because an etch stop layer has an etch rate substantially smaller than that of an insulation interlayer formed on the etch stop layer. Since the lower portion of the lower electrode has the substantially small inner diameter, a dielectric layer and an upper electrode formed on the lower electrode may not be efficiently formed. Thus, a leakage current may be generated. In addition, a device failure may occur. Accordingly, the reliability and yield of the semiconductor device such as a DRAM may unfortunately decrease.